The present invention relates to a method for fabricating an electrode structure including a lower film of polysilicon or amorphous silicon and an upper film of a metal with a high melting point, and a method for fabricating a semiconductor device including the electrode structure as a gate electrode.
In a conventional MOS transistor, the gate electrode is formed from a polysilicon film. In accordance with refinement and increase in operation speed of LSIS, there are increasing demands for lowering resistance of a gate electrode of a MOS transistor.
For the purpose of lowering the resistance of a gate electrode, technique to use, as a gate electrode, a polymetal gate electrode of a multi-layer film including a lower polysilicon film and an upper metal film with a high melting point is proposed, and a tungsten film is proposed for use as the upper metal film with a high melting point. When a tungsten film is used as the upper metal film with a high melting point, the resistance of the gate electrode can be lowered.
It is necessary to form, between the polysilicon film and the tungsten film, a barrier film of tungsten nitride (WN,) or titanium nitride (TiN) for preventing a dopant (such as B, P and As) introduced into the polysilicon film from diffusing into the tungsten film (as described in, for example, Japanese Laid-Open Patent Publication Nos. 11-261059 and 7-235542).
FIG. 8A shows the cross-sectional structure of an electrode structure according to a first conventional example. As shown in FIG. 8A, a gate electrode is formed above a semiconductor substrate 1 with a gate insulating film 2 sandwiched therebetween, and the gate electrode is composed of a polysilicon film 3, a barrier film 4A of tungsten nitride (WNx) and a tungsten film 5 successively formed in this order in the upward direction.
FIG. 8B shows the cross-sectional structure of an electrode structure according to a second conventional example. As shown in FIG. 8B, a gate electrode is formed above a semiconductor substrate 1 with a gate insulating film 2 sandwiched therebetween, and the gate electrode is composed of a polysilicon film 3, a barrier film 4B of titanium nitride (TiN) and a tungsten film 5 successively formed in this order in the upward direction.
In the electrode structure of the first conventional example, when annealing is carried out in a subsequent procedure, nitrogen included in the barrier film 4A of tungsten nitride is evaporated, so that the barrier film 4A can be changed into the tungsten film 5. In addition, nitrogen included in the barrier film 4A is reacted with silicon included in the polysilicon film 3, so that a reaction layer 6 of silicon nitride (SiN) with very high resistance can be formed between the polysilicon film 3 and the tungsten film 5 as shown in FIG. 8C. As a result, the resistance of the gate electrode is disadvantageously increased.
As a countermeasure, Japanese Laid-Open Patent Publication No. 7-235542 describes that the sheet resistance of the reaction layer 6 can be lowered so as to lower the resistance of the gate electrode by setting the surface density of nitrogen included in the reaction layer 6 of silicon nitride to a predetermined value or less.
The present inventors, however, have found that the resistance of the gate electrode cannot be lowered even when the surface density of nitrogen included in the reaction layer 6 is set to the predetermined value or less in the electrode structure of the first conventional example.
Therefore, the present inventors have variously examined why the resistance of the gate electrode cannot be lowered in the electrode structure of the first conventional example, resulting in finding the following: When the thickness of the barrier film 4A is reduced to approximately 0.1 through 1.0 nm for lowering the surface density of nitrogen included in the reaction layer 6, the barrier film 4A cannot exhibit the barrier function and tungsten silicide (WSix) is formed, and hence, the resistance of the gate electrode cannot be lowered. On the other hand, when the thickness of the barrier film 4A is larger than 1.0 nm, although the barrier function can be exhibited, the reaction layer 6 of silicon nitride with very high resistance is formed between the polysilicon film 3 and the tungsten film 5. Therefore, the interface resistance between the polysilicon film 3 and the tungsten film 5 is increased.
Furthermore, since the tungsten nitride film has poor heat resistance, a large amount of nitrogen included in the tungsten nitride film is diffused through annealing carried out at 750xc2x0 C. or more, so as to change the tungsten nitride film into a tungsten film.
In the case where the barrier film of titanium nitride is used as in the electrode structure of the second conventional example, a reaction layer 6 of silicon nitride with very high resistance is formed between the polysilicon film and the tungsten film. Therefore, the interface resistance between the polysilicon film 3 and the tungsten film 5 is increased.
As shown in FIG. 9A, a polysilicon film 3 is formed above a semiconductor substrate 1 with a gate insulating film 2 sandwiched therebetween, and the polysilicon film 3 is doped with a p-type dopant such as boron in forming a p-type gate electrode and with an n-type dopant such as phosphorus in forming an n-type gate electrode. In order to deposit a titanium nitride film 4B on the polysilicon film 3, the semiconductor substrate 1 is placed in a chamber in which a titanium target 7 including titanium as a principal constituent is disposed. Then, a mixed gas of an argon gas and a nitrogen gas is introduced into the chamber and discharge is caused in the chamber. In this manner, plasma is generated from the argon gas and the nitrogen gas, and nitrogen ions included in the plasma are reacted with silicon included in the polysilicon film 3, so that a reaction layer 6 of silicon nitride can be formed in a surface portion of the polysilicon film 3. The titanium target 7 is also nitrided so as to form a titanium nitride film 8 thereon, and titanium nitride is sputtered out from the titanium nitride film 8 so as to form a barrier film 4B of titanium nitride on the reaction layer 6 as shown in FIG. 9B.
Then, the semiconductor substrate 1 is placed in a chamber in which a tungsten target 9 including tungsten as a principal constituent is disposed, an argon gas is introduced into the chamber and discharge is caused in the chamber. In this manner, plasma is generated from the argon gas, and tungsten is sputtered out from the tungsten target 9 by argon ions included in the plasma, so that the sputtered tungsten can be deposited on the titanium nitride film 4B. As a result, a tungsten film 5 is formed on the titanium nitride film 4B as shown in FIG. 9C.
Next, dopant layers serving as a source and a drain of the MOS transistor are formed in the semiconductor substrate 1, and annealing is carried out at 750xc2x0 C. or more for activating the dopant layers. Thus, excessive nitrogen included in the barrier film 4B is diffused into an upper portion of the polysilicon film 3 as shown in FIG. 10A. As a result, the thickness of the reaction layer 6 of titanium nitride is increased as shown in FIG. 10B.
Also, the present inventors have examined the relationship between the annealing temperature and the interface resistance of the barrier film obtained after the annealing. FIG. 11 shows the relationship between the annealing temperature (xc2x0 C.) and the interface resistance (Rc) between the polysilicon film and the metal film with a high melting point obtained after the annealing. In FIG. 11, the relationship obtained when a barrier film of tungsten nitride (WNx) is formed on an n-type polysilicon film (expressed as NPS) is plotted with xe2x97xaf, the relationship obtained when a barrier film of tungsten nitride is formed on a p-type polysilicon film (expressed as PPS) is plotted with ◯, the relationship obtained when a barrier film of titanium nitride (TiN) is formed on an n-type polysilicon film is plotted with ♦, and the relationship obtained when a barrier film of titanium nitride is formed on a p-type polysilicon film is plotted with ⋄. Also, in FIG. 11, since the contact between the films is non-ohmic, the interface resistance is shown as a resistance value obtained by allowing a current of 1 mA/xcexcm2 to flow.
It is understood from FIG. 11 that the interface resistance is high in using the barrier film 4B of titanium nitride even when the annealing is carried out at a low temperature. Also, as a result of experiments made by the present inventors, it is found that the interface resistance is high in using the barrier film 4B of titanium nitride even when the annealing is not carried out. This is because the reaction layer 6 is formed between the polysilicon film 3 and the barrier film 4B as shown in FIGS. 9A through 9C.
Furthermore, in using the barrier film 4A of tungsten nitride, although the interface resistance is lower than in using the barrier film 4B of titanium nitride, the interface resistance is abruptly increased when the annealing is carried out at 750xc2x0 C. or more. This is because in using the barrier film 4A of tungsten nitride, nitrogen included in the tungsten nitride is diffused through the annealing carried out at 750xc2x0 C. or more, so as to form the reaction layer 6 of silicon nitride between the polysilicon film 3 and the tungsten film 5.
When the interface resistance (Rc) between the polysilicon film 3 and the tungsten film 5 is high, the operation speed of the MOS transistor is lowered. Specifically, when the gate electrode is operated with AC (alternating current), distributed capacitance generated in the gate insulating film is repeatedly charged and discharged. Therefore, a current flows through distributed interface resistance, and hence, the influence of the distributed interface resistance is exhibited, which lowers the operation speed of the MOS transistor. When the operation speed of the MOS transistor is lowered, the operation speed of the entire LSI is lowered, so as to disadvantageously increase signal delay time. Since the operation speed of an LSI is regarded to be the most significant today, the lowering of the operation speed of the MOS transistor by merely several % becomes a serious problem.
In order to lower the interface resistance so as not to affect the delay time of the MOS transistor, interface resistance of 300 xcexa9xcexcm2 or less should be attained.
In consideration of the aforementioned conventional disadvantages, an object of the invention is lowering interface resistance between a polysilicon film and a metal film with a high melting point.
In order to achieve the object, the method for fabricating an electrode structure of this invention comprises the steps of depositing a first metal film of a first metal on a silicon-containing film containing silicon as a principal constituent; depositing a second metal film of a nitride of a second metal on the first metal film; depositing a metal film with a high melting point on the second metal film, whereby forming a multi-layer film of the silicon-containing film, the first metal film, the second metal film and the metal film with a high melting point; and carrying out annealing on the multi-layer film at a temperature of 750xc2x0 C. or more, and the first metal is nitrided to be changed into a nitride of the first metal before the annealing, and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing.
In the method for fabricating an electrode structure of this invention, a barrier film composed of the lower first metal film of the first metal and the upper second metal film of the nitride of the second metal is disposed between the silicon-containing film and the metal film with a high melting point. Furthermore, the first metal is changed into the nitride of the first metal and a silicide layer of the first metal is not formed in a surface portion of the silicon-containing film before the annealing. Therefore, the interface resistance between the silicon-containing film and the metal film with a high melting point is largely lowered for the following reason: Nitrogen included in the second metal film is consumed in nitriding the first metal film, and merely a small amount of nitrogen included in the second metal film is used for nitriding the silicon-containing film. Accordingly, a reaction layer of a silicon nitride film formed between the silicon-containing film and the metal nitride film and having very high resistance can be reduced in its thickness, which lowers the interface resistance.
In the method for fabricating an electrode structure, no silicon nitride film or a silicon nitride film with a thickness of 1.5 nm or less is preferably formed between the silicon-containing film and the first metal film as a result of the annealing.
In this manner, the interface resistance between the silicon-containing film and the metal film with a high melting point can be suppressed to 300 xcexa9xcexcm2 or less. Therefore, the delay time of a MOS transistor including a gate electrode composed of the electrode structure of this invention can be largely reduced.
In the method for fabricating an electrode structure, interface resistance between the silicon-containing film and the metal film with a high melting point is preferably 300 xcexa9xcexcm2 or less after the annealing.
In this manner, the delay time of a MOS transistor including a gate electrode composed of the electrode structure of this invention can be largely reduced.
In the method for fabricating an electrode structure, it is preferred that the first metal and the second metal are the same metal, that the first metal film is deposited through sputtering carried out by using a target including the same metal, and that the second metal film is deposited by sputtering a nitride film of the same metal formed in a surface portion of the target.
In this manner, the first metal film and the second metal film can be continuously deposited by using the target of the same metal with merely an introduced gas changed, resulting in improving the throughput.
In the method for fabricating an electrode structure, the first metal and the second metal are preferably both titanium.
In the method for fabricating an electrode structure, the nitride of the second metal can be titanium nitride, tungsten nitride, tantalum nitride or tungsten silicide nitride.
In order to achieve the object, the method for fabricating a semiconductor device of this invention comprises the steps of depositing a polysilicon film on a semiconductor region; depositing a first metal film of a first metal on the polysilicon film; depositing a second metal film of a nitride of a second metal on the first metal film; depositing a metal film with a high melting point on the second metal film, whereby forming a gate electrode including the polysilicon film, the first metal film, the second metal film and the metal film with a high melting point; forming dopant layers serving as a source and a drain by ion implanting a dopant with the gate electrode used as a mask; and activating the dopant layers by carrying out annealing at a temperature of 750xc2x0 C. or more, and the first metal is nitrided to be changed into a nitride of the first metal before the annealing, and a silicide layer of the first metal is not formed in a surface portion of the polysilicon film before the annealing.
In the method for fabricating a semiconductor device of this invention, a semiconductor device is fabricated by employing the method for fabricating an electrode structure of this invention. Therefore, even when the annealing at 750xc2x0 C. or more is carried out for activating the dopant layers serving as the source and the drain, the interface resistance between the polysilicon film and the metal film with a high melting point included in the gate electrode can be very low.
Accordingly, the delay time of the MOS transistor can be reduced so as to improve the operation speed of the MOS transistor.
In the method for fabricating a semiconductor device, no silicon nitride film or a silicon nitride film with a thickness of 1.5 nm or less is preferably formed between the polysilicon film and the first metal film as a result of the annealing.
In this manner, the delay time of the MOS transistor can be largely reduced.
In the method for fabricating a semiconductor device, the first metal and the second metal are preferably both titanium.